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<p>XEfusePl is the PL eFUSE driver instance.
 <a href="struct_xil_s_key___e_pl.html#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a1b59c48cecc611c8bcebfd5d3c771e2b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a1b59c48cecc611c8bcebfd5d3c771e2b">ForcePowerCycle</a></td></tr>
<tr class="memdesc:a1b59c48cecc611c8bcebfd5d3c771e2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following are the FUSE CNTRL bits[1:5, 8-10].  <a href="#a1b59c48cecc611c8bcebfd5d3c771e2b">More...</a><br/></td></tr>
<tr class="separator:a1b59c48cecc611c8bcebfd5d3c771e2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a774ab7699dcc7f98e2fa6ecad1e8f756"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a774ab7699dcc7f98e2fa6ecad1e8f756">KeyWrite</a></td></tr>
<tr class="memdesc:a774ab7699dcc7f98e2fa6ecad1e8f756"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE will disable eFUSE write to FUSE_AES and FUSE_USER blocks valid only for zynq but in ultrascale If XTRUE will disable eFUSE write to FUSE_AESKEY block in Ultrascale.  <a href="#a774ab7699dcc7f98e2fa6ecad1e8f756">More...</a><br/></td></tr>
<tr class="separator:a774ab7699dcc7f98e2fa6ecad1e8f756"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a711c95684db2e41a869d10459d88e9b1"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a711c95684db2e41a869d10459d88e9b1">AESKeyRead</a></td></tr>
<tr class="memdesc:a711c95684db2e41a869d10459d88e9b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE will disable eFUSE read to FUSE_AES block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in Zynq Pl.but in Ultrascale if XTRUE will disable eFUSE read to FUSE_KEY block and also disables eFUSE write to FUSE_KEY blocks.  <a href="#a711c95684db2e41a869d10459d88e9b1">More...</a><br/></td></tr>
<tr class="separator:a711c95684db2e41a869d10459d88e9b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5538ca40d23c65ee020b4470ce049e0c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a5538ca40d23c65ee020b4470ce049e0c">UserKeyRead</a></td></tr>
<tr class="memdesc:a5538ca40d23c65ee020b4470ce049e0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in zynq but in ultrascale if XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_USER blocks.  <a href="#a5538ca40d23c65ee020b4470ce049e0c">More...</a><br/></td></tr>
<tr class="separator:a5538ca40d23c65ee020b4470ce049e0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a196329dc81109234ef4f1edd57a01880"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a196329dc81109234ef4f1edd57a01880">CtrlWrite</a></td></tr>
<tr class="memdesc:a196329dc81109234ef4f1edd57a01880"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE will disable eFUSE write to FUSE_CNTRL block in both Zynq and Ultrascale.  <a href="#a196329dc81109234ef4f1edd57a01880">More...</a><br/></td></tr>
<tr class="separator:a196329dc81109234ef4f1edd57a01880"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4cbfec6ccb5280bd9260ae15441a6271"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a4cbfec6ccb5280bd9260ae15441a6271">RSARead</a></td></tr>
<tr class="memdesc:a4cbfec6ccb5280bd9260ae15441a6271"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE will disable eFuse read to FUSE_RSA block and also disables eFuse write to FUSE_RSA block in Ultrascale.  <a href="#a4cbfec6ccb5280bd9260ae15441a6271">More...</a><br/></td></tr>
<tr class="separator:a4cbfec6ccb5280bd9260ae15441a6271"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aab8339da7263b300324db20a3ee72724"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#aab8339da7263b300324db20a3ee72724">UserKeyWrite</a></td></tr>
<tr class="memdesc:aab8339da7263b300324db20a3ee72724"><td class="mdescLeft">&#160;</td><td class="mdescRight">only For Ultrascale  <a href="#aab8339da7263b300324db20a3ee72724">More...</a><br/></td></tr>
<tr class="separator:aab8339da7263b300324db20a3ee72724"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ada22f99111140d11cc67226569376f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a4ada22f99111140d11cc67226569376f">SecureWrite</a></td></tr>
<tr class="memdesc:a4ada22f99111140d11cc67226569376f"><td class="mdescLeft">&#160;</td><td class="mdescRight">only For Ultrascale  <a href="#a4ada22f99111140d11cc67226569376f">More...</a><br/></td></tr>
<tr class="separator:a4ada22f99111140d11cc67226569376f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9729ef3c149797740d10822b39b19018"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a9729ef3c149797740d10822b39b19018">RSAWrite</a></td></tr>
<tr class="memdesc:a9729ef3c149797740d10822b39b19018"><td class="mdescLeft">&#160;</td><td class="mdescRight">only For Ultrascale  <a href="#a9729ef3c149797740d10822b39b19018">More...</a><br/></td></tr>
<tr class="separator:a9729ef3c149797740d10822b39b19018"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5967e09149546718390b703241026c82"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a5967e09149546718390b703241026c82">User128BitWrite</a></td></tr>
<tr class="memdesc:a5967e09149546718390b703241026c82"><td class="mdescLeft">&#160;</td><td class="mdescRight">If TRUE will disable eFUSE write to 128BIT FUSE_USER block in Ultrascale.  <a href="#a5967e09149546718390b703241026c82">More...</a><br/></td></tr>
<tr class="separator:a5967e09149546718390b703241026c82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a86a44bd882e3545554782a10e6e3ccad"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a86a44bd882e3545554782a10e6e3ccad">SecureRead</a></td></tr>
<tr class="memdesc:a86a44bd882e3545554782a10e6e3ccad"><td class="mdescLeft">&#160;</td><td class="mdescRight">IF XTRUE will disable eFuse read to FUSE_SEC block and also disables eFuse write to FUSE_SEC block in Ultrascale.  <a href="#a86a44bd882e3545554782a10e6e3ccad">More...</a><br/></td></tr>
<tr class="separator:a86a44bd882e3545554782a10e6e3ccad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa8accba02c9a494c07e8961af0d66f91"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#aa8accba02c9a494c07e8961af0d66f91">AESKeyExclusive</a></td></tr>
<tr class="memdesc:aa8accba02c9a494c07e8961af0d66f91"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE will force eFUSE key to be used if booting Secure Image In Zynq.  <a href="#aa8accba02c9a494c07e8961af0d66f91">More...</a><br/></td></tr>
<tr class="separator:aa8accba02c9a494c07e8961af0d66f91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae8d6993d65619202c4f26b0201beabd2"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ae8d6993d65619202c4f26b0201beabd2">JtagDisable</a></td></tr>
<tr class="memdesc:ae8d6993d65619202c4f26b0201beabd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE then permanently sets the Zynq ARM DAP controller in bypass mode in both zynq and ultrascale.  <a href="#ae8d6993d65619202c4f26b0201beabd2">More...</a><br/></td></tr>
<tr class="separator:ae8d6993d65619202c4f26b0201beabd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac13e638ed18908b22a6f9655149d23f8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ac13e638ed18908b22a6f9655149d23f8">UseAESOnly</a></td></tr>
<tr class="memdesc:ac13e638ed18908b22a6f9655149d23f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE will force to use Secure boot with eFUSE key only for both Zynq and Ultrascale.  <a href="#ac13e638ed18908b22a6f9655149d23f8">More...</a><br/></td></tr>
<tr class="separator:ac13e638ed18908b22a6f9655149d23f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aab3257952c815e823614a6006dbace38"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#aab3257952c815e823614a6006dbace38">EncryptOnly</a></td></tr>
<tr class="memdesc:aab3257952c815e823614a6006dbace38"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE will only allow encrypted bitstreams only.  <a href="#aab3257952c815e823614a6006dbace38">More...</a><br/></td></tr>
<tr class="separator:aab3257952c815e823614a6006dbace38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3e9b2dfd9d2c0bb6f229379a35e12bd0"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a3e9b2dfd9d2c0bb6f229379a35e12bd0">IntTestAccessDisable</a></td></tr>
<tr class="memdesc:a3e9b2dfd9d2c0bb6f229379a35e12bd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE then sets the disable's Xilinx internal test access in Ultrascale.  <a href="#a3e9b2dfd9d2c0bb6f229379a35e12bd0">More...</a><br/></td></tr>
<tr class="separator:a3e9b2dfd9d2c0bb6f229379a35e12bd0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5774c588ee1a0ea1ad3d041015fa7043"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a5774c588ee1a0ea1ad3d041015fa7043">DecoderDisable</a></td></tr>
<tr class="memdesc:a5774c588ee1a0ea1ad3d041015fa7043"><td class="mdescLeft">&#160;</td><td class="mdescRight">If XTRUE then permanently disables the decryptor in Ultrascale.  <a href="#a5774c588ee1a0ea1ad3d041015fa7043">More...</a><br/></td></tr>
<tr class="separator:a5774c588ee1a0ea1ad3d041015fa7043"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8e307477f877e9cfe590d48938cf0641"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a8e307477f877e9cfe590d48938cf0641">RSAEnable</a></td></tr>
<tr class="memdesc:a8e307477f877e9cfe590d48938cf0641"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable RSA authentication in ultrascale.  <a href="#a8e307477f877e9cfe590d48938cf0641">More...</a><br/></td></tr>
<tr class="separator:a8e307477f877e9cfe590d48938cf0641"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6b3ef36f911c7b13d5a41a08abe0bfee"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a6b3ef36f911c7b13d5a41a08abe0bfee">FuseObfusEn</a></td></tr>
<tr class="memdesc:a6b3ef36f911c7b13d5a41a08abe0bfee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Obfuscated feature for decryption of eFUSE AES.  <a href="#a6b3ef36f911c7b13d5a41a08abe0bfee">More...</a><br/></td></tr>
<tr class="separator:a6b3ef36f911c7b13d5a41a08abe0bfee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aff5241ec33acd90c43a890de5cb5a436"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#aff5241ec33acd90c43a890de5cb5a436">ProgAESandUserLowKey</a></td></tr>
<tr class="memdesc:aff5241ec33acd90c43a890de5cb5a436"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to select AES key and User Low Key for Zynq.  <a href="#aff5241ec33acd90c43a890de5cb5a436">More...</a><br/></td></tr>
<tr class="separator:aff5241ec33acd90c43a890de5cb5a436"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a602174fd48e8a64b3d3b17d265bfebe8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a602174fd48e8a64b3d3b17d265bfebe8">ProgUserHighKey</a></td></tr>
<tr class="memdesc:a602174fd48e8a64b3d3b17d265bfebe8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to select User Low Key for Zynq.  <a href="#a602174fd48e8a64b3d3b17d265bfebe8">More...</a><br/></td></tr>
<tr class="separator:a602174fd48e8a64b3d3b17d265bfebe8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a107defbe48daf538934109698094c593"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a107defbe48daf538934109698094c593">ProgAESKeyUltra</a></td></tr>
<tr class="memdesc:a107defbe48daf538934109698094c593"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to select User key for Ultrascale.  <a href="#a107defbe48daf538934109698094c593">More...</a><br/></td></tr>
<tr class="separator:a107defbe48daf538934109698094c593"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa3847b2035f72162f03c24341aeb3f74"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#aa3847b2035f72162f03c24341aeb3f74">ProgUserKeyUltra</a></td></tr>
<tr class="memdesc:aa3847b2035f72162f03c24341aeb3f74"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to select User key for Ultrascale.  <a href="#aa3847b2035f72162f03c24341aeb3f74">More...</a><br/></td></tr>
<tr class="separator:aa3847b2035f72162f03c24341aeb3f74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad937f035079a6feae899c34ee3b53fcc"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ad937f035079a6feae899c34ee3b53fcc">ProgRSAKeyUltra</a></td></tr>
<tr class="memdesc:ad937f035079a6feae899c34ee3b53fcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to select RSA key for Ultrascale.  <a href="#ad937f035079a6feae899c34ee3b53fcc">More...</a><br/></td></tr>
<tr class="separator:ad937f035079a6feae899c34ee3b53fcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4a0372b19cab30cde15c54da188a0224"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a4a0372b19cab30cde15c54da188a0224">ProgUser128BitUltra</a></td></tr>
<tr class="memdesc:a4a0372b19cab30cde15c54da188a0224"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to program 128 bit User key for Ultrascale.  <a href="#a4a0372b19cab30cde15c54da188a0224">More...</a><br/></td></tr>
<tr class="separator:a4a0372b19cab30cde15c54da188a0224"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d38ca57c12c5b32ba4647206874bf99"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a9d38ca57c12c5b32ba4647206874bf99">CheckAESKeyUltra</a></td></tr>
<tr class="memdesc:a9d38ca57c12c5b32ba4647206874bf99"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to read AES key for Ultrascale.  <a href="#a9d38ca57c12c5b32ba4647206874bf99">More...</a><br/></td></tr>
<tr class="separator:a9d38ca57c12c5b32ba4647206874bf99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a20f1a57abc56693ad01407de88393a73"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a20f1a57abc56693ad01407de88393a73">ReadUserKeyUltra</a></td></tr>
<tr class="memdesc:a20f1a57abc56693ad01407de88393a73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to read User key for Ultrascale.  <a href="#a20f1a57abc56693ad01407de88393a73">More...</a><br/></td></tr>
<tr class="separator:a20f1a57abc56693ad01407de88393a73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1ccd65d13cb719bcf3fdc437a983f530"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a1ccd65d13cb719bcf3fdc437a983f530">ReadRSAKeyUltra</a></td></tr>
<tr class="memdesc:a1ccd65d13cb719bcf3fdc437a983f530"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to read RSA key for Ultrascale.  <a href="#a1ccd65d13cb719bcf3fdc437a983f530">More...</a><br/></td></tr>
<tr class="separator:a1ccd65d13cb719bcf3fdc437a983f530"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7723fdbadd052ca1c51026e257fd5bc6"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a7723fdbadd052ca1c51026e257fd5bc6">ReadUser128BitUltra</a></td></tr>
<tr class="memdesc:a7723fdbadd052ca1c51026e257fd5bc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Following is the define to select if the user wants to read 128 bit User key for Ultrascale.  <a href="#a7723fdbadd052ca1c51026e257fd5bc6">More...</a><br/></td></tr>
<tr class="separator:a7723fdbadd052ca1c51026e257fd5bc6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa2faee19a31db87af9a53673566f2f13"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#aa2faee19a31db87af9a53673566f2f13">AESKey</a> [XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES]</td></tr>
<tr class="memdesc:aa2faee19a31db87af9a53673566f2f13"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is the REF_CLK value in Hz.  <a href="#aa2faee19a31db87af9a53673566f2f13">More...</a><br/></td></tr>
<tr class="separator:aa2faee19a31db87af9a53673566f2f13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a38dd51b5e9ad3cdc7a28b375f76d26c0"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a38dd51b5e9ad3cdc7a28b375f76d26c0">UserKey</a> [XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES]</td></tr>
<tr class="memdesc:a38dd51b5e9ad3cdc7a28b375f76d26c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is for the user_key value.  <a href="#a38dd51b5e9ad3cdc7a28b375f76d26c0">More...</a><br/></td></tr>
<tr class="separator:a38dd51b5e9ad3cdc7a28b375f76d26c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a54e3f92351b5dcc194ec5457958e031f"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a54e3f92351b5dcc194ec5457958e031f">RSAKeyHash</a> [XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES]</td></tr>
<tr class="memdesc:a54e3f92351b5dcc194ec5457958e031f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is for the rsa_key value for Ultrascale.  <a href="#a54e3f92351b5dcc194ec5457958e031f">More...</a><br/></td></tr>
<tr class="separator:a54e3f92351b5dcc194ec5457958e031f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a063cfa4b21e1b383cd83ad325b8e64ed"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a063cfa4b21e1b383cd83ad325b8e64ed">User128Bit</a> [XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES]</td></tr>
<tr class="memdesc:a063cfa4b21e1b383cd83ad325b8e64ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is for the User 128 bit key value for Ultrascale.  <a href="#a063cfa4b21e1b383cd83ad325b8e64ed">More...</a><br/></td></tr>
<tr class="separator:a063cfa4b21e1b383cd83ad325b8e64ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2776f357478d389408d232913c1cbb53"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a2776f357478d389408d232913c1cbb53">JtagMioTDI</a></td></tr>
<tr class="memdesc:a2776f357478d389408d232913c1cbb53"><td class="mdescLeft">&#160;</td><td class="mdescRight">TDI MIO Pin Number for ZYNQ.  <a href="#a2776f357478d389408d232913c1cbb53">More...</a><br/></td></tr>
<tr class="separator:a2776f357478d389408d232913c1cbb53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af8f9f0570d4bfc7acacee027586f5e56"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#af8f9f0570d4bfc7acacee027586f5e56">JtagMioTDO</a></td></tr>
<tr class="memdesc:af8f9f0570d4bfc7acacee027586f5e56"><td class="mdescLeft">&#160;</td><td class="mdescRight">TDO MIO Pin Number for ZYNQ.  <a href="#af8f9f0570d4bfc7acacee027586f5e56">More...</a><br/></td></tr>
<tr class="separator:af8f9f0570d4bfc7acacee027586f5e56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a96ac0343e25d5018afdf244e151b5774"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a96ac0343e25d5018afdf244e151b5774">JtagMioTCK</a></td></tr>
<tr class="memdesc:a96ac0343e25d5018afdf244e151b5774"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCK MIO Pin Number for ZYNQ.  <a href="#a96ac0343e25d5018afdf244e151b5774">More...</a><br/></td></tr>
<tr class="separator:a96ac0343e25d5018afdf244e151b5774"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aba077864dc5eaae499c2248fac346f25"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#aba077864dc5eaae499c2248fac346f25">JtagMioTMS</a></td></tr>
<tr class="memdesc:aba077864dc5eaae499c2248fac346f25"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMS MIO Pin Number for ZYNQ.  <a href="#aba077864dc5eaae499c2248fac346f25">More...</a><br/></td></tr>
<tr class="separator:aba077864dc5eaae499c2248fac346f25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5df47267442068ab0ed0246010b830eb"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a5df47267442068ab0ed0246010b830eb">JtagMioMuxSel</a></td></tr>
<tr class="memdesc:a5df47267442068ab0ed0246010b830eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">MUX Selection MIO Pin Number for ZYNQ.  <a href="#a5df47267442068ab0ed0246010b830eb">More...</a><br/></td></tr>
<tr class="separator:a5df47267442068ab0ed0246010b830eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a591d57563de0bf3d53980b2044668838"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a591d57563de0bf3d53980b2044668838">JtagMuxSelLineDefVal</a></td></tr>
<tr class="memdesc:a591d57563de0bf3d53980b2044668838"><td class="mdescLeft">&#160;</td><td class="mdescRight">Value on the MUX Selection line for ZYNQ.  <a href="#a591d57563de0bf3d53980b2044668838">More...</a><br/></td></tr>
<tr class="separator:a591d57563de0bf3d53980b2044668838"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada4028ad814145b1809a2f88898aaecd"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ada4028ad814145b1809a2f88898aaecd">JtagGpioID</a></td></tr>
<tr class="memdesc:ada4028ad814145b1809a2f88898aaecd"><td class="mdescLeft">&#160;</td><td class="mdescRight">GPIO device ID.  <a href="#ada4028ad814145b1809a2f88898aaecd">More...</a><br/></td></tr>
<tr class="separator:ada4028ad814145b1809a2f88898aaecd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a56d91ced464348fec8f2a8fbce77bb7a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a56d91ced464348fec8f2a8fbce77bb7a">HwmGpioStart</a></td></tr>
<tr class="memdesc:a56d91ced464348fec8f2a8fbce77bb7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hardware module Start signal's GPIO pin number.  <a href="#a56d91ced464348fec8f2a8fbce77bb7a">More...</a><br/></td></tr>
<tr class="separator:a56d91ced464348fec8f2a8fbce77bb7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae55857a70dba305506c52fba852110ac"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ae55857a70dba305506c52fba852110ac">HwmGpioReady</a></td></tr>
<tr class="memdesc:ae55857a70dba305506c52fba852110ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hardware module Ready signal's GPIO pin number.  <a href="#ae55857a70dba305506c52fba852110ac">More...</a><br/></td></tr>
<tr class="separator:ae55857a70dba305506c52fba852110ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac202d3a966a769834389ff7c6290b35d"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ac202d3a966a769834389ff7c6290b35d">HwmGpioEnd</a></td></tr>
<tr class="memdesc:ac202d3a966a769834389ff7c6290b35d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hardware module End signal's GPIO pin number.  <a href="#ac202d3a966a769834389ff7c6290b35d">More...</a><br/></td></tr>
<tr class="separator:ac202d3a966a769834389ff7c6290b35d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae75b1daf8df1029358e5a15ab9bc26fe"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ae75b1daf8df1029358e5a15ab9bc26fe">JtagGpioTDI</a></td></tr>
<tr class="memdesc:ae75b1daf8df1029358e5a15ab9bc26fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">TDI AXI GPIO pin number for Ultrascale.  <a href="#ae75b1daf8df1029358e5a15ab9bc26fe">More...</a><br/></td></tr>
<tr class="separator:ae75b1daf8df1029358e5a15ab9bc26fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4134bce2ab39d2d47673f291dcce73c2"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a4134bce2ab39d2d47673f291dcce73c2">JtagGpioTDO</a></td></tr>
<tr class="memdesc:a4134bce2ab39d2d47673f291dcce73c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">TDO AXI GPIO pin number for Ultrascale.  <a href="#a4134bce2ab39d2d47673f291dcce73c2">More...</a><br/></td></tr>
<tr class="separator:a4134bce2ab39d2d47673f291dcce73c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a05f212c85ea8dbd450f600aa21e6e8ed"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a05f212c85ea8dbd450f600aa21e6e8ed">JtagGpioTMS</a></td></tr>
<tr class="memdesc:a05f212c85ea8dbd450f600aa21e6e8ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMS AXI GPIO pin number for Ultrascale.  <a href="#a05f212c85ea8dbd450f600aa21e6e8ed">More...</a><br/></td></tr>
<tr class="separator:a05f212c85ea8dbd450f600aa21e6e8ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0d11eb75b7c39d9dc0e78f024d614537"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a0d11eb75b7c39d9dc0e78f024d614537">JtagGpioTCK</a></td></tr>
<tr class="memdesc:a0d11eb75b7c39d9dc0e78f024d614537"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCK AXI GPIO pin number for Ultrascale.  <a href="#a0d11eb75b7c39d9dc0e78f024d614537">More...</a><br/></td></tr>
<tr class="separator:a0d11eb75b7c39d9dc0e78f024d614537"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aab5460f2ce046d0465e58816aee2ec4c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#aab5460f2ce046d0465e58816aee2ec4c">GpioInputCh</a></td></tr>
<tr class="memdesc:aab5460f2ce046d0465e58816aee2ec4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI GPIO Channel number of all Inputs TDO.  <a href="#aab5460f2ce046d0465e58816aee2ec4c">More...</a><br/></td></tr>
<tr class="separator:aab5460f2ce046d0465e58816aee2ec4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a48f629a0d571b0446bef0bdf880838b3"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a48f629a0d571b0446bef0bdf880838b3">GpioOutPutCh</a></td></tr>
<tr class="memdesc:a48f629a0d571b0446bef0bdf880838b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI GPIO Channel number for all Outputs TDI/TMS/TCK.  <a href="#a48f629a0d571b0446bef0bdf880838b3">More...</a><br/></td></tr>
<tr class="separator:a48f629a0d571b0446bef0bdf880838b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad985a52bc03fb6c518d69bc408993a16"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ad985a52bc03fb6c518d69bc408993a16">AESKeyReadback</a> [XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES]</td></tr>
<tr class="memdesc:ad985a52bc03fb6c518d69bc408993a16"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES key read only for Zynq.  <a href="#ad985a52bc03fb6c518d69bc408993a16">More...</a><br/></td></tr>
<tr class="separator:ad985a52bc03fb6c518d69bc408993a16"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac87e2861138039e830dbd7135dcd7f10"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ac87e2861138039e830dbd7135dcd7f10">UserKeyReadback</a> [XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES]</td></tr>
<tr class="memdesc:ac87e2861138039e830dbd7135dcd7f10"><td class="mdescLeft">&#160;</td><td class="mdescRight">User key read in Ultrascale and Zynq.  <a href="#ac87e2861138039e830dbd7135dcd7f10">More...</a><br/></td></tr>
<tr class="separator:ac87e2861138039e830dbd7135dcd7f10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afa9047760ff4bc90ba35d87fab6c3f92"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#afa9047760ff4bc90ba35d87fab6c3f92">CrcOfAESKey</a></td></tr>
<tr class="memdesc:afa9047760ff4bc90ba35d87fab6c3f92"><td class="mdescLeft">&#160;</td><td class="mdescRight">Expected AES key's CRC for Ultrascale here we can't read AES key directly.  <a href="#afa9047760ff4bc90ba35d87fab6c3f92">More...</a><br/></td></tr>
<tr class="separator:afa9047760ff4bc90ba35d87fab6c3f92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad8c001614e2da159f22cca4a8177313f"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#ad8c001614e2da159f22cca4a8177313f">AESKeyMatched</a></td></tr>
<tr class="memdesc:ad8c001614e2da159f22cca4a8177313f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag is True is AES's CRC is matched, otherwise False.  <a href="#ad8c001614e2da159f22cca4a8177313f">More...</a><br/></td></tr>
<tr class="separator:ad8c001614e2da159f22cca4a8177313f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9a0d5ef04ec9687a70291766b687524e"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a9a0d5ef04ec9687a70291766b687524e">RSAHashReadback</a> [XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES]</td></tr>
<tr class="memdesc:a9a0d5ef04ec9687a70291766b687524e"><td class="mdescLeft">&#160;</td><td class="mdescRight">RSA key read back for Ultrascale.  <a href="#a9a0d5ef04ec9687a70291766b687524e">More...</a><br/></td></tr>
<tr class="separator:a9a0d5ef04ec9687a70291766b687524e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a299adba0c12ba9e0862f4ccff2a2a85b"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a299adba0c12ba9e0862f4ccff2a2a85b">User128BitReadBack</a> [XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES]</td></tr>
<tr class="memdesc:a299adba0c12ba9e0862f4ccff2a2a85b"><td class="mdescLeft">&#160;</td><td class="mdescRight">User 128 bit key read back for Ultrascale.  <a href="#a299adba0c12ba9e0862f4ccff2a2a85b">More...</a><br/></td></tr>
<tr class="separator:a299adba0c12ba9e0862f4ccff2a2a85b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8986470536a340a600dd4f7413f24278"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a8986470536a340a600dd4f7413f24278">SystemInitDone</a></td></tr>
<tr class="memdesc:a8986470536a340a600dd4f7413f24278"><td class="mdescLeft">&#160;</td><td class="mdescRight">Internal variable to check if timer, XADC and JTAG are initialized.  <a href="#a8986470536a340a600dd4f7413f24278">More...</a><br/></td></tr>
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<tr class="memitem:a38866931c81a58e00bcc5ddb97bc480f"><td class="memItemLeft" align="right" valign="top">XSKEfusePl_Fpga&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a38866931c81a58e00bcc5ddb97bc480f">FpgaFlag</a></td></tr>
<tr class="memdesc:a38866931c81a58e00bcc5ddb97bc480f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stores Fpga series of Efuse.  <a href="#a38866931c81a58e00bcc5ddb97bc480f">More...</a><br/></td></tr>
<tr class="separator:a38866931c81a58e00bcc5ddb97bc480f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b3ccd58ca8df92062ffcf357c287723"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a2b3ccd58ca8df92062ffcf357c287723">CrcToVerify</a></td></tr>
<tr class="memdesc:a2b3ccd58ca8df92062ffcf357c287723"><td class="mdescLeft">&#160;</td><td class="mdescRight">CRC of AES key to verify programmed AES key.  <a href="#a2b3ccd58ca8df92062ffcf357c287723">More...</a><br/></td></tr>
<tr class="separator:a2b3ccd58ca8df92062ffcf357c287723"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9822db41ea7dafc7f6228f4993f290c8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a9822db41ea7dafc7f6228f4993f290c8">NumSlr</a></td></tr>
<tr class="memdesc:a9822db41ea7dafc7f6228f4993f290c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of SLRs to iterate through.  <a href="#a9822db41ea7dafc7f6228f4993f290c8">More...</a><br/></td></tr>
<tr class="separator:a9822db41ea7dafc7f6228f4993f290c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4b9a790a0d2ce5fee937ab96fc48cb54"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#a4b9a790a0d2ce5fee937ab96fc48cb54">MasterSlr</a></td></tr>
<tr class="memdesc:a4b9a790a0d2ce5fee937ab96fc48cb54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current SLR to iterate through.  <a href="#a4b9a790a0d2ce5fee937ab96fc48cb54">More...</a><br/></td></tr>
<tr class="separator:a4b9a790a0d2ce5fee937ab96fc48cb54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa5d097fa213f877bd730d56f061f524d"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_s_key___e_pl.html#aa5d097fa213f877bd730d56f061f524d">SlrConfigOrderIndex</a></td></tr>
<tr class="memdesc:aa5d097fa213f877bd730d56f061f524d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slr configuration order Index.  <a href="#aa5d097fa213f877bd730d56f061f524d">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>XEfusePl is the PL eFUSE driver instance. </p>
<p>Using this structure, user can define the eFUSE bits to be blown. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="aa2faee19a31db87af9a53673566f2f13"></a>
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<p>This is the REF_CLK value in Hz. </p>
<p>&lt; u32 RefClk; This is for the aes_key valuefor both Zynq and Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<p>If XTRUE will force eFUSE key to be used if booting Secure Image In Zynq. </p>
<p>Only for Zynq </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<p>Flag is True is AES's CRC is matched, otherwise False. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

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<a class="anchor" id="a711c95684db2e41a869d10459d88e9b1"></a>
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<p>If XTRUE will disable eFUSE read to FUSE_AES block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in Zynq Pl.but in Ultrascale if XTRUE will disable eFUSE read to FUSE_KEY block and also disables eFUSE write to FUSE_KEY blocks. </p>
<p>For Zynq and Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="ad985a52bc03fb6c518d69bc408993a16"></a>
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          <td class="memname">u8 XilSKey_EPl::AESKeyReadback[XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES]</td>
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<p>AES key read only for Zynq. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

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          <td class="memname">u32 XilSKey_EPl::CheckAESKeyUltra</td>
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<p>Following is the define to select if the user wants to read AES key for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<div class="memproto">
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          <td class="memname">u32 XilSKey_EPl::CrcOfAESKey</td>
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<p>Expected AES key's CRC for Ultrascale here we can't read AES key directly. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

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          <td class="memname">u32 XilSKey_EPl::CrcToVerify</td>
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<p>CRC of AES key to verify programmed AES key. </p>
<p>Only for Ultrascale </p>

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<p>If XTRUE will disable eFUSE write to FUSE_CNTRL block in both Zynq and Ultrascale. </p>
<p>For Zynq and Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<p>If XTRUE then permanently disables the decryptor in Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<p>If XTRUE will only allow encrypted bitstreams only. </p>
<p>For Ultrascale only </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a1b59c48cecc611c8bcebfd5d3c771e2b"></a>
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          <td class="memname">u32 XilSKey_EPl::ForcePowerCycle</td>
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<p>Following are the FUSE CNTRL bits[1:5, 8-10]. </p>
<p>If XTRUE then part has to be power cycled to be able to be reconfigured only for zynqOnly for ZYNQ </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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          <td class="memname">XSKEfusePl_Fpga XilSKey_EPl::FpgaFlag</td>
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<p>Stores Fpga series of Efuse. </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

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<a class="anchor" id="a6b3ef36f911c7b13d5a41a08abe0bfee"></a>
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          <td class="memname">u32 XilSKey_EPl::FuseObfusEn</td>
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<p>Enable Obfuscated feature for decryption of eFUSE AES. </p>
<p>only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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          <td class="memname">u32 XilSKey_EPl::GpioInputCh</td>
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<p>AXI GPIO Channel number of all Inputs TDO. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a48f629a0d571b0446bef0bdf880838b3"></a>
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          <td class="memname">u32 XilSKey_EPl::GpioOutPutCh</td>
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<p>AXI GPIO Channel number for all Outputs TDI/TMS/TCK. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="ac202d3a966a769834389ff7c6290b35d"></a>
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          <td class="memname">u32 XilSKey_EPl::HwmGpioEnd</td>
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<p>Hardware module End signal's GPIO pin number. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="ae55857a70dba305506c52fba852110ac"></a>
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          <td class="memname">u32 XilSKey_EPl::HwmGpioReady</td>
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<p>Hardware module Ready signal's GPIO pin number. </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a56d91ced464348fec8f2a8fbce77bb7a"></a>
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<p>Hardware module Start signal's GPIO pin number. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a3e9b2dfd9d2c0bb6f229379a35e12bd0"></a>
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          <td class="memname">u32 XilSKey_EPl::IntTestAccessDisable</td>
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<p>If XTRUE then sets the disable's Xilinx internal test access in Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="ae8d6993d65619202c4f26b0201beabd2"></a>
<div class="memitem">
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<p>If XTRUE then permanently sets the Zynq ARM DAP controller in bypass mode in both zynq and ultrascale. </p>
<p>for Zynq and Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="ada4028ad814145b1809a2f88898aaecd"></a>
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          <td class="memname">u32 XilSKey_EPl::JtagGpioID</td>
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<p>GPIO device ID. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a0d11eb75b7c39d9dc0e78f024d614537"></a>
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          <td class="memname">u32 XilSKey_EPl::JtagGpioTCK</td>
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<p>TCK AXI GPIO pin number for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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</div>
<a class="anchor" id="ae75b1daf8df1029358e5a15ab9bc26fe"></a>
<div class="memitem">
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          <td class="memname">u32 XilSKey_EPl::JtagGpioTDI</td>
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<p>TDI AXI GPIO pin number for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a4134bce2ab39d2d47673f291dcce73c2"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">u32 XilSKey_EPl::JtagGpioTDO</td>
        </tr>
      </table>
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<p>TDO AXI GPIO pin number for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="a05f212c85ea8dbd450f600aa21e6e8ed"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">u32 XilSKey_EPl::JtagGpioTMS</td>
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      </table>
</div><div class="memdoc">

<p>TMS AXI GPIO pin number for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a5df47267442068ab0ed0246010b830eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::JtagMioMuxSel</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MUX Selection MIO Pin Number for ZYNQ. </p>
<p>Only for ZYNQ </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a96ac0343e25d5018afdf244e151b5774"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::JtagMioTCK</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TCK MIO Pin Number for ZYNQ. </p>
<p>Only for ZYNQ </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a2776f357478d389408d232913c1cbb53"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::JtagMioTDI</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TDI MIO Pin Number for ZYNQ. </p>
<p>Only for ZYNQ </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="af8f9f0570d4bfc7acacee027586f5e56"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::JtagMioTDO</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TDO MIO Pin Number for ZYNQ. </p>
<p>Only for ZYNQ </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="aba077864dc5eaae499c2248fac346f25"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::JtagMioTMS</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMS MIO Pin Number for ZYNQ. </p>
<p>Only for ZYNQ </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a591d57563de0bf3d53980b2044668838"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::JtagMuxSelLineDefVal</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Value on the MUX Selection line for ZYNQ. </p>
<p>Only for ZYNQ </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a774ab7699dcc7f98e2fa6ecad1e8f756"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::KeyWrite</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>If XTRUE will disable eFUSE write to FUSE_AES and FUSE_USER blocks valid only for zynq but in ultrascale If XTRUE will disable eFUSE write to FUSE_AESKEY block in Ultrascale. </p>
<p>For ZYNQ and Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a4b9a790a0d2ce5fee937ab96fc48cb54"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::MasterSlr</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Current SLR to iterate through. </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>.</p>

</div>
</div>
<a class="anchor" id="a9822db41ea7dafc7f6228f4993f290c8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::NumSlr</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Number of SLRs to iterate through. </p>

<p>Referenced by <a class="el" href="xilskey__jscmd_8c.html#ae229739e4765d3ed48b18e529764bdfe">JtagServerInit()</a>, and <a class="el" href="xilskey__efuse__example_8c.html#ae66f6b31b5ad750f1fe042a706a4e3d4">main()</a>.</p>

</div>
</div>
<a class="anchor" id="aff5241ec33acd90c43a890de5cb5a436"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::ProgAESandUserLowKey</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Following is the define to select if the user wants to select AES key and User Low Key for Zynq. </p>
<p>Only for Zynq </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a107defbe48daf538934109698094c593"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::ProgAESKeyUltra</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Following is the define to select if the user wants to select User key for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="ad937f035079a6feae899c34ee3b53fcc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::ProgRSAKeyUltra</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Following is the define to select if the user wants to select RSA key for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a4a0372b19cab30cde15c54da188a0224"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::ProgUser128BitUltra</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Following is the define to select if the user wants to program 128 bit User key for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a602174fd48e8a64b3d3b17d265bfebe8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::ProgUserHighKey</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Following is the define to select if the user wants to select User Low Key for Zynq. </p>
<p>Only for Zynq </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="aa3847b2035f72162f03c24341aeb3f74"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::ProgUserKeyUltra</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Following is the define to select if the user wants to select User key for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a1ccd65d13cb719bcf3fdc437a983f530"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::ReadRSAKeyUltra</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Following is the define to select if the user wants to read RSA key for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a7723fdbadd052ca1c51026e257fd5bc6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::ReadUser128BitUltra</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Following is the define to select if the user wants to read 128 bit User key for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a20f1a57abc56693ad01407de88393a73"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::ReadUserKeyUltra</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Following is the define to select if the user wants to read User key for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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</div>
<a class="anchor" id="a8e307477f877e9cfe590d48938cf0641"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::RSAEnable</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable RSA authentication in ultrascale. </p>
<p>only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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</div>
<a class="anchor" id="a9a0d5ef04ec9687a70291766b687524e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u8 XilSKey_EPl::RSAHashReadback[XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES]</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RSA key read back for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

</div>
</div>
<a class="anchor" id="a54e3f92351b5dcc194ec5457958e031f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u8 XilSKey_EPl::RSAKeyHash[XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES]</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This is for the rsa_key value for Ultrascale. </p>
<p>Only for Ultrascale </p>

</div>
</div>
<a class="anchor" id="a4cbfec6ccb5280bd9260ae15441a6271"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::RSARead</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>If XTRUE will disable eFuse read to FUSE_RSA block and also disables eFuse write to FUSE_RSA block in Ultrascale. </p>
<p>only For Ultrascale If XTRUE will disable eFUSE write to FUSE_USER block in Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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</div>
<a class="anchor" id="a9729ef3c149797740d10822b39b19018"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::RSAWrite</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>only For Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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</div>
<a class="anchor" id="a86a44bd882e3545554782a10e6e3ccad"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::SecureRead</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>IF XTRUE will disable eFuse read to FUSE_SEC block and also disables eFuse write to FUSE_SEC block in Ultrascale. </p>
<p>only For Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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</div>
<a class="anchor" id="a4ada22f99111140d11cc67226569376f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::SecureWrite</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>only For Ultrascale </p>
<p>If XTRUE will disable eFUSE write to FUSE_RSA block in Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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<a class="anchor" id="aa5d097fa213f877bd730d56f061f524d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::SlrConfigOrderIndex</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slr configuration order Index. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#ae66f6b31b5ad750f1fe042a706a4e3d4">main()</a>.</p>

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</div>
<a class="anchor" id="a8986470536a340a600dd4f7413f24278"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::SystemInitDone</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Internal variable to check if timer, XADC and JTAG are initialized. </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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</div>
<a class="anchor" id="ac13e638ed18908b22a6f9655149d23f8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::UseAESOnly</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>If XTRUE will force to use Secure boot with eFUSE key only for both Zynq and Ultrascale. </p>
<p>For Zynq and Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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</div>
<a class="anchor" id="a063cfa4b21e1b383cd83ad325b8e64ed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u8 XilSKey_EPl::User128Bit[XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES]</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This is for the User 128 bit key value for Ultrascale. </p>
<p>Only for Ultrascale </p>

</div>
</div>
<a class="anchor" id="a299adba0c12ba9e0862f4ccff2a2a85b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u8 XilSKey_EPl::User128BitReadBack[XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES]</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>User 128 bit key read back for Ultrascale. </p>
<p>Only for Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

</div>
</div>
<a class="anchor" id="a5967e09149546718390b703241026c82"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::User128BitWrite</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>If TRUE will disable eFUSE write to 128BIT FUSE_USER block in Ultrascale. </p>
<p>only For Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a38dd51b5e9ad3cdc7a28b375f76d26c0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u8 XilSKey_EPl::UserKey[XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES]</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This is for the user_key value. </p>
<p>for both Zynq and Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

</div>
</div>
<a class="anchor" id="a5538ca40d23c65ee020b4470ce049e0c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">u32 XilSKey_EPl::UserKeyRead</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>If XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in zynq but in ultrascale if XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_USER blocks. </p>
<p>For Zynq and Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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          <td class="memname">u8 XilSKey_EPl::UserKeyReadback[XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES]</td>
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<p>User key read in Ultrascale and Zynq. </p>
<p>for Ultrascale and Zynq </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a4ea026a1ab321b06be36cf1cb5192148">XilSKey_EfusePl_ReadnCheck()</a>.</p>

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          <td class="memname">u32 XilSKey_EPl::UserKeyWrite</td>
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<p>only For Ultrascale </p>
<p>If XTRUE will disable eFUSE write to FUSE_SEC block in Ultrascale </p>

<p>Referenced by <a class="el" href="xilskey__efuse__example_8c.html#a862b8c5897a66fabd7bc5bb3c9b4723c">XilSKey_EfusePl_InitData()</a>.</p>

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